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<div class="textblock"><p>The <a class="el" href="struct_x_sys_mon.html" title="The driver&#39;s instance data. ">XSysMon</a> driver supports the Xilinx System Monitor/ADC device.The System Monitor/ADC device has the following features:</p><ul>
<li>10-bit, 200-KSPS (kilo samples per second) Analog-to-Digital Converter (ADC)</li>
<li>Monitoring of on-chip supply voltages and temperature</li>
<li>1 dedicated differential analog-input pair and 16 auxiliary differential analog-input pairs</li>
<li>Automatic alarms based on user defined limits for the on-chip supply voltages and temperature</li>
<li>Automatic Channel Sequencer, programmable averaging, programmable acquisition time for the external inputs, unipolar or differential input selection for the external inputs</li>
<li>Inbuilt Calibration</li>
<li>Optional interrupt request generation</li>
<li>External Mux (7 Series and Zynq XADC)</li>
</ul>
<p>The user should refer to the hardware device specification for detailed information about the device.</p>
<p>This header file contains the prototypes of driver functions that can be used to access the System Monitor/ADC device.</p>
<p><b> System Monitor Channel Sequencer Modes </b></p>
<p>The System Monitor Channel Sequencer supports the following operating modes:</p>
<ul>
<li><b> Default </b>: This is the default mode after power up. In this mode of operation the System Monitor operates in a sequence mode, monitoring the on chip sensors: Temperature, VCCINT, and VCCAUX.</li>
<li><b> One pass through sequence </b>: In this mode the System Monitor converts the channels enabled in the Sequencer Channel Enable registers for a single pass and then stops.</li>
<li><b> Continuous cycling of sequence </b>: In this mode the System Monitor converts the channels enabled in the Sequencer Channel Enable registers continuously.</li>
<li><b> Single channel mode</b>: In this mode the System Monitor Channel Sequencer is disabled and the System Monitor operates in a Single Channel Mode. The System Monitor can operate either in a Continuous or Event driven sampling mode in the single channel mode.</li>
<li><b> Simultaneous sampling mode</b>: This mode is available only in 7 Series and Zynq XADC devices. In this mode both ADCs sample and digitizes two different analog input signals at the same time.</li>
<li><b> Independent ADC mode</b>: This mode is available only in 7 Series and Zynq XADC devices. In this mode ADC A is used to implement a fixed monitoring mode which is similar to default mode, but the fixed alarm functions are enabled. ADC B is available to be used with the external analog input channels only.</li>
</ul>
<p><b> Initialization and Configuration </b></p>
<p>The device driver enables higher layer software (e.g., an application) to communicate to the System Monitor/ADC device.</p>
<p><a class="el" href="group__sysmon__v7__1.html#ga543ff01a3a1c5b625c2b874cbb809465" title="This function initializes a specific XSysMon device/instance. ">XSysMon_CfgInitialize()</a> API is used to initialize the System Monitor/ADC device. The user needs to first call the <a class="el" href="group__sysmon__v7__1.html#gaf2f837d4a34ab56e268078a2874389d4" title="Functions in xsysmon_sinit.c. ">XSysMon_LookupConfig()</a> API which returns the Configuration structure pointer which is passed as a parameter to the <a class="el" href="group__sysmon__v7__1.html#ga543ff01a3a1c5b625c2b874cbb809465" title="This function initializes a specific XSysMon device/instance. ">XSysMon_CfgInitialize()</a> API.</p>
<p><b>Interrupts</b></p>
<p>The System Monitor/ADC device supports interrupt driven mode and the default operation mode is polling mode.</p>
<p>The interrupt mode is available only if hardware is configured to support interrupts.</p>
<p>This driver does not provide a Interrupt Service Routine (ISR) for the device. It is the responsibility of the application to provide one if needed. Refer to the interrupt example provided with this driver for details on using the device in interrupt mode.</p>
<p><b> Virtual Memory </b></p>
<p>This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.</p>
<p><b> Threads </b></p>
<p>This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.</p>
<p><b> Asserts </b></p>
<p>Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.</p>
<p><b> Building the driver </b></p>
<p>The <a class="el" href="struct_x_sys_mon.html" title="The driver&#39;s instance data. ">XSysMon</a> driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.</p>
<p><b> Limitations of the driver </b></p>
<p>System Monitor/ADC device can be accessed through the JTAG port and the AXI interface. The driver implementation does not support the simultaneous access of the device by both these interfaces. The user has to care of this situation in the user application code.</p>
<p><br />
<br />
</p>
<pre></pre><pre>MODIFICATION HISTORY:</pre><pre>Ver   Who    Date     Changes
----- -----  -------- -----------------------------------------------------
1.00a xd/sv  05/22/07 First release
2.00a sv     07/07/08 Added bit definitions for new Alarm Interrupts in the
		Interrupt Registers. Changed the ADC data functions
		to return 16 bits of data. Added macros for conversion
		from Raw Data to Temperature/Voltage and vice-versa.
3.00a sdm    02/09/09 Added APIs and bit definitions for V6 SysMon.
4.00a ktn    10/22/09 Updated the driver to use the HAL Processor APIs/macros.
	        The macros have been renamed to remove _m from the name
	        in all the driver files.
5.00a sdm    06/15/11 Added support for XADC 7 Series.
5.01a bss    02/28/12 Added support for Zynq,
		renamed XSM_ATR_BRAM_UPPER to XSM_ATR_VBRAM_UPPER
		renamed XSM_ATR_BRAM_LOWER to XSM_ATR_VBRAM_LOWER
5.02a bss    11/23/12 Added APIs and Macros to support Temperature Updation
		over TEMP_OUT port(CR #679872)
5.03a bss    04/25/13 Modified XSysMon_SetSeqChEnables,
		XSysMon_SetSeqAvgEnables, XSysMon_SetSeqInputMode
		and XSysMon_SetSeqAcqTime APIs to check for Safe Mode
		instead of Single Channel mode(CR #703729) in <a class="el" href="xsysmon_8c.html">xsysmon.c</a>
		Modified examples: xsysmon_polled_example.c,
		xsysmon_low_level_example.c,
		xsysmon_intr_printf_example.c, xsysmon_intr_example.c
		xsysmon_extmux_example.c and
		xsysmon_polled_printf_example.c to set Sequencer Mode
		as Safe mode instead of Single channel mode before
		configuring Sequencer registers.
6.0   adk  19/12/13   Updated as per the New Tcl API's
7.0   bss  7/25/14    To support Ultrascale:
		Added XSM_CH_VUSR0 - XSMXSM_CH_VUSR3,XSM_MAX_VUSR0 -
		XSM_MIN_VUSR3,XSM_ATR_VUSR0_UPPER -
		XSM_ATR_VUSR3_LOWER macros.
		Added XSM_IP_OFFSET macro(since register
		offsets are different for Ultrascale comapared to
		earlier familes),Offsets,Masks for VUSER0 to
		VUSER3 channels, Configuration Register 3 and
		Sequence Registers 8 and 9 in <a class="el" href="xsysmon__hw_8h.html">xsysmon_hw.h</a>.
		Modified XSysMon_GetAdcData,
		XSysMon_GetMinMaxMeasurement,
		XSysMon_SetSingleChParams, XSysMon_SetAlarmEnables,
		XSysMon_GetAlarmEnables,XSysMon_SetSeqChEnables,
		XSysMon_GetSeqChEnables,XSysMon_SetSeqAvgEnables,
		XSysMon_GetSeqAvgEnables,XSysMon_SetAlarmThreshold
		and XSysMon_GetAlarmThreshold in <a class="el" href="xsysmon_8c.html">xsysmon.c</a>.
		Modified driver tcl to generate XPAR_SYSMON_0_IP_TYPE
		parameter.
7.1	bss  05/06/15 Modified temperature transfer function for
					  for Ultrascale CR#859369
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